The present invention is related to the forming of improved contacts between interconnect layers in integrated circuits and is particularly useful in the production of very large scale integrated circuits.
Contact between metal interconnect layers in multi-layer integrated circuits is provided by via holes through a dielectric layer between the metal interconnect layers. Sputter deposited aluminum is the most commonly used interconnect material; however, the sputtering technique does not provide completely conformal step coverage, to include the steps which comprise vias holes. The sputtered film will typically be thinner on vertical surfaces than it is on horizontal surfaces. This is particularly true where the steps have steep vertical slopes or negative slopes. Electromigration of the metal atoms under the influence of electric current may form voids in the thinner portions of the metal film to the point that an open occurs and the via contact can no longer carry current. The electromigration phenomenon increases with current density and temperature, and its effects are cumulative.
When there is a high aspect ratio between the thickness of the dielectric layers to the diameter of the via holes, metal sputter deposited over the dielectric layers collects around the upper edges of the via holes, choking off the via holes such that metal cannot enter the via hole to completely form a via contact having electrical integrity through the dielectric layer from the upper metal interconnect layer to the lower metal interconnect layer. This condition is referred herein as a re-entrant condition. This re-entrant condition becomes more serious as relatively thicker dielectric layers and smaller diameter via holes become more common to limit electrical interference between layers in multi-layer integrated circuit chips.
In the paper "A Planar Metallization Process--Its Application to Tri-level Aluminum Interconnection" by T. Moriya et al., pages 550-553, IEDM83, a method of refilling via holes with tungsten by selective chemical vapor deposition is discussed. Among other substrate materials, tungsten is deposited on aluminum and aluminum-silicon alloy having 1% silicon. It is noted, at page 551 of the article that in the case of tungsten deposited directly on an aluminum-silicon alloy, flourine is observed to pile up at the interface making the contact resistivity relatively high considering the metal-to-metal structure. This high resistivity is not desirable in the forming of interlayer contacts. To reduce the contact resistivity in the disclosed process, a thin layer of MoSi.sub.2 is sputter deposited on top of the AlSi alloy before the interlayer insulator deposition.
In the article "Refractory Metal Silicides: Thin-Film Properties and Processing Technology", T. Paul Chow et al, IEEE Transactions on Electron Devices, Vol. ED-30, No. 11, November 1983, at page 1486, the deposition of metal over silicon areas suitable in VLSI technology is suggested.
In a paper entitled "Low Pressure Chemical Vapor Deposition of Metals and Their Application in VLSI Technology" by Eliot K. Broadbent, presented at the Electrochemical Society Meeting, Washington, D.C., Oct. 9-14, 1983, the author discussed selective CVD tungsten via/contact filling wherein via holes through an oxide layer is filled by the selective chemical vapor deposition of tungsten.
In an abstract titled "Tungsten Selective Deposition Part 2: Tungsten Selective Self-Alignment Gate Technology" by P. A. Gargini et al., Abstract No. 381, ECS Fall 1981, the forming of a gate structure utilizing a low resistance tungsten film on top of polysilicon is discussed.
U.S. Pat. No. 3,632,436 issued Jan. 4, 1972 to Denning for "Contact System for Semiconductor Devices" discloses a method for forming a nickel-lead contact system which includes depositing a thin film of nickel electrolessly on a silicon layer, but not on an underlaying oxide layer.
In U.S. Pat. No. 4,330,931 issued May 25, 1982 to Liu for "Process for Forming Metal Plated Regions and Lines in MOS Circuits" a process for forming self-aligned, metal plated substrate regions and polysilicon members is described in which a tungsten deposition is used to form metal plating over exposed substrate regions and over a polysilicon member, with no metal being formed over adjacent oxide lips.
U.S. Pat. No. 4,507,853 issued Apr. 2, 1985 to McDavid for "Metallization Process for Integrated Circuits" discloses metal contacts and interconnections for semiconductor integrated circuits formed by a two metal deposition process. A first metal layer is deposited over a step or the sidewalls of an aperture, and then a preferential etch removes all of the first metal layer except on the vertical side of the step or aperture. Silicon exposed at the bottom of the aperture is used as an etch stop. A second layer of metal is deposited over the integrated circuit, including the remaining parts of the first metal layer, in gross, and not selectively.
U.S. Patents which show the state of the art include: U.S. Pat. No. 3,653,120 issued Apr. 4, 1972 to Sirrine et al. for "Method of Making Low Resistance Polycrystalline Silicon Contacts to Buried Collector Regions Using Refractory Metal Silicides"; U.S. Pat. No. 3,887,993 issued June 10, 1975 to Okada et al. for "Method of Making an Ohmic Contact with a Semiconductor Substrate"; U.S. Pat. No. 4,248,688 issued Feb. 3, 1981 to Gartner et al. for "Ion Milling of Thin Metal Films"; U.S. Pat. No. 4,259,680 issued Mar. 31, 1981 to Lepselter et al. for "High Speed Lateral Bipolar Transistor"; U.S. Pat. No. 4,267,012 issued May 12, 1981 to Pierce et al. for "Process for Patterning Metal Connections On A Semiconductor Structure by Using a Tungsten-Titanium Etch Resistant Layer"; U.S. Pat. No. 4,273,859 issued June 16, 1981 to Mones et al. for "Method of Forming Solder Bump Terminals on Semiconductor Elements"; U.S. Pat. No. 4,329,706 issued May 11, 1982 to Crowder et al. for "Doped Polysilicon Silicide Semiconductor Integrated Circuit Interconnections"; U.S. Pat. No. 4,356,622 issued Nov. 2, 1982 to Widmann for "Method of Producing Low-Resistance Diffused Regions in IC MOS Semiconductor Circuits In Silicon-Gate Technology Metal Silicide Layer Formation"; U.S. Pat. No. 4,358,891 issued Nov. 16, 1982 to Roesner for "Method of Forming A Metal Semiconductor Field Effect Transistor"; and U.S. Pat. No. 4,374,700 issued Feb. 22, 1983 to Scott et al for "Method of Manufacturing Silicide Contacts for CMOS Devices".